Introduction

This help document is intended to provide in-depth information and reference material specific to your digitizer product.

For information on getting started with your digitizer, please refer to the Startup Guide which was delivered with your product or may be downloaded from the Keysight Technologies website.

Contents:

Notices & General Information

Introduction

Front Panel Features

Channel Input

Data Acquisition

Trigger

External Clock & Reference

Calibration

Trigger Output

Multi-Purpose Inputs and Outputs

Delay Controls

Signal Processing (Firmware Options)

M9703A Hardware Extension of 89600 VSA Software

Multi-Module Synchronization

Electrical, Environmental & Physical Specifications

Programming Information

Utilities

Accessories

© Keysight Technologies 2012 - 2015

Part No: M9703-90005

Version: 3

Wednesday, September 23, 2015


Notices

© Keysight Technologies, 2012 - 2015

No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Keysight Technologies, Inc. as governed by United States and international copyright laws.

Manual Part Number

M9703-90005

Support

To contact Keysight for sales and technical support, refer to the “support” links on the following Keysight web resources:

www.keysight.com/find/digitizers - Home page for the entire range of Keysight modular digitizer products.

www.keysight.com/find/assist - Worldwide contact information for repair and service.

www.keysight.com - Information on preventing damage to your Keysight equipment.

Regulatory Compliance

This product has been designed and tested in accordance with accepted industry standards, and has been supplied in a safe condition. To review the Declaration of Conformity, go to http://www.keysight.com/go/conformity .

Warranty

The material contained in this document is provided “as is,” and is subject to being changed, without notice, in future editions. Further, to the maximum extent permitted by applicable law, Keysight disclaims all warranties, either express or implied, with regard to this manual and any information contained herein, including but not limited to the implied warranties of merchantability and fitness for a particular purpose. Keysight shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein. Should Keysight and the user have a separate written agreement with warranty terms covering the material in this document that conflict with these terms, the warranty terms in the separate agreement shall control.

Keysight Technologies does not warrant third-party system-level (combination of chassis, controllers, modules, etc.) performance, safety, or regulatory compliance, unless specifically stated.

Technology Licenses

The hardware and/or software described in this document are furnished under a license and may be used or copied only in accordance with the terms of such license.

U.S. Government Rights

The Software is “commercial computer software,” as defined by Federal Acquisition Regulation (“FAR”) 2.101. Pursuant to FAR 12.212 and 27.405-3 and Department of Defense FAR Supplement (“DFARS”) 227.7202, the U.S. government acquires commercial computer software under the same terms by which the software is customarily provided to the public. Accordingly, Keysight provides the Software to U.S. government customers under its standard commercial license, which is embodied in its End User License Agreement (EULA), a copy of which can be found at http://www.keysight.com/find/sweula. The license set forth in the EULA represents the exclusive authority by which the U.S. government may use, modify, distribute, or disclose the Software. The EULA and the license set forth therein, does not require or permit, among other things, that Keysight: (1) Furnish technical information related to commercial computer software or commercial computer software documentation that is not customarily provided to the public; or (2) Relinquish to, or otherwise provide, the government rights in excess of these rights customarily provided to the public to use, modify, reproduce, release, perform, display, or disclose commercial computer software or commercial computer software documentation. No additional government requirements beyond those set forth in the EULA shall apply, except to the extent that those terms, rights, or licenses are explicitly required from all providers of commercial computer software pursuant to the FAR and the DFARS and are set forth specifically in writing elsewhere in the EULA. Keysight shall be under no obligation to update, revise or otherwise modify the Software. With respect to any technical data as defined by FAR 2.101, pursuant to FAR 12.211 and 27.404.2 and DFARS 227.7102, the U.S. government acquires no greater than Limited Rights as defined in FAR 27.401 or DFAR 227.7103-5 (c), as applicable in any technical data.

Conventions Used in this Document

The following conventions are used in this document:

A WARNING notice denotes a hazard. It calls attention to an operating procedure, practice, or the like that, if not correctly performed or adhered to, could result in personal injury or death. Do not proceed beyond a WARNING notice until the indicated conditions are fully understood and met.

A Caution notice denotes a hazard. It calls attention to an operating procedure, practice, or the like that, if not correctly performed or adhered to, could result in damage to the product or loss of important data. Do not proceed beyond a CAUTION notice until the indicated conditions are fully understood and met

This is a note, drawing the reader's attention to important information, caveats, etc.

'Italic' text denotes a reference to a quoted name or entity. e.g."Press the 'Run' button."

Bold Italic text is used to emphasize an important action point in the text. e.g. "Open the View menu and select the All option."

mono text is used for sections of code, programming examples and operating system commands. e.g. "Type the command >> Run -all"

Underlined Italic text denotes paths or file names. e.g. "The file is located in the folder, e.g...\Keysight\MD2\.."

Safety Notices

The following safety precautions should be observed before using this product and any associated instrumentation.

This product is intended for use by qualified personnel who recognize shock hazards and are familiar with the safety precautions required to avoid possible injury. Read and follow all installation, operation, and maintenance information carefully before using the product.

If this product is not used as specified, the protection provided by the equipment could be impaired. This product must be used in a normal condition (in which all means for protection are intact) only.

The types of product users are:

  • Responsible body is the individual or group responsible for the use and maintenance of equipment, for ensuring that the equipment is operated within its specifications and operating limits, and for ensuring operators are adequately trained.
  • Operators use the product for its intended function. They must be trained in electrical safety procedures and proper use of the instrument. They must be protected from electric shock and contact with hazardous live circuits.
  • Maintenance personnel perform routine procedures on the product to keep it operating properly (for example, setting the line voltage or replacing consumable materials). Maintenance procedures are described in the user documentation. The procedures explicitly state if the operator may perform them. Otherwise, they should be performed only by service personnel.
  • Service personnel are trained to work on live circuits, perform safe installations, and repair products. Only properly trained service personnel may perform installation and service procedures.

Operator is responsible to maintain safe operating conditions. To ensure safe operating conditions, modules should not be operated beyond the full temperature range specified in the Environmental and physical specification. Exceeding safe operating conditions can result in shorter lifespans, improper module performance and user safety issues. When the modules are in use and operation within the specified full temperature range is not maintained, module surface temperatures may exceed safe handling conditions which can cause discomfort or burns if touched. In the event of a module exceeding the full temperature range, always allow the module to cool before touching or removing modules from chassis.

Keysight products are designed for use with electrical signals that are rated Measurement Category I and Measurement Category II, as described in the International Electrotechnical Commission (IEC) Standard IEC 60664. Most measurement, control, and data I/O signals are Measurement Category I and must not be directly connected to mains voltage or to voltage sources with high transient over-voltages. Measurement Category II connections require protection for high transient over-voltages often associated with local AC mains connections. Assume all measurement, control, and data I/O connections are for connection to Category I sources unless otherwise marked or described in the user documentation.

Exercise extreme caution when a shock hazard is present. Lethal voltage may be present on cable connector jacks or test fixtures. The American National Standards Institute (ANSI) states that a shock hazard exists when voltage levels greater than 30V RMS, 42.4V peak, or 60VDC are present. A good safety practice is to expect that hazardous voltage is present in any unknown circuit before measuring.

Operators of this product must be protected from electric shock at all times. The responsible body must ensure that operators are prevented access and/or insulated from every connection point. In some cases, connections must be exposed to potential human contact. Product operators in these circumstances must be trained to protect themselves from the risk of electric shock. If the circuit is capable of operating at or above 1000V, no conductive part of the circuit may be exposed.

Do not connect switching cards directly to unlimited power circuits. They are intended to be used with impedance-limited sources. NEVER connect switching cards directly to AC mains. When connecting sources to switching cards, install protective devices to limit fault current and voltage to the card.

Before operating an instrument, ensure that the line cord is connected to a properly-grounded power receptacle. Inspect the connecting cables, test leads, and jumpers for possible wear, cracks, or breaks before each use.

When installing equipment where access to the main power cord is restricted, such as rack mounting, a separate main input power disconnect device must be provided in close proximity to the equipment and within easy reach of the operator.

For maximum safety, do not touch the product, test cables, or any other instruments while power is applied to the circuit under test. ALWAYS remove power from the entire test system and discharge any capacitors before: connecting or disconnecting cables or jumpers, installing or removing switching cards, or making internal changes, such as installing or removing jumpers.

Do not touch any object that could provide a current path to the common side of the circuit under test or power line (earth) ground. Always make measurements with dry hands while standing on a dry, insulated surface capable of withstanding the voltage being measured.

The instrument and accessories must be used in accordance with its specifications and operating instructions, or the safety of the equipment may be impaired.

Do not exceed the maximum signal levels of the instruments and accessories, as defined in the specifications and operating information, and as shown on the instrument or test fixture panels, or switching card.

When fuses are used in a product, replace with the same type and rating for continued protection against fire hazard.

Chassis connections must only be used as shield connections for measuring circuits, NOT as safety earth ground connections.

If you are using a test fixture, keep the lid closed while power is applied to the device under test. Safe operation requires the use of a lid interlock.

Instrumentation and accessories shall not be connected to humans.

Before performing any maintenance, disconnect the line cord and all test cables.

To maintain protection from electric shock and fire, replacement components in mains circuits – including the power transformer, test leads, and input jacks – must be purchased from Keysight. Standard fuses with applicable national safety approvals may be used if the rating and type are the same. Other components that are not safety-related may be purchased from other suppliers as long as they are equivalent to the original component (note that selected parts should be purchased only through Keysight to maintain accuracy and functionality of the product). If you are unsure about the applicability of a replacement component, call an Keysight office for information.

No operator serviceable parts inside. Refer servicing to qualified personnel. To prevent electrical shock do not remove covers. For continued protection against fire hazard, replace fuse with same type and rating.

PRODUCT MARKINGS:

The CE mark is a registered trademark of the European Community.

Australian Communication and Media Authority mark to indicate regulatory compliance as a registered supplier.

This symbol indicates product compliance with the Canadian Interference-Causing Equipment Standard (ICES-001). It also identifies the product is an Industrial Scientific and Medical Group 1 Class A product (CISPR 11, Clause 4).

South Korean Class A EMC Declaration. this equipment is Class A suitable for professional use and is for use in electromagnetic environments outside of the home.

A 급 기기 ( 업무용 방송통신기자재 ) 이 기기는 업무용 (A 급 ) 전자파적합기기로서 판 매자 또는 사용자는 이 점을 주 의하시기 바라 며 , 가정외의 지역에서 사용하는 것을 목적으 로 합니다 .

This product complies with the WEEE Directive marketing requirement. The affixed product label (above) indicates that you must not discard this electrical/electronic product in domestic household waste. Product Category: With reference to the equipment types in the WEEE directive Annex 1, this product is classified as “Monitoring and Control instrumentation” product. Do not dispose in domestic household waste. To return unwanted products, contact your local Keysight office, or for more information see http://about.keysight.com/en/companyinfo/environment/takeback.shtml.

This symbol on an instrument means caution, risk of danger. You should refer to the operating instructions located in the user documentation in all cases where the symbol is marked on the instrument.

This symbol indicates the time period during which no hazardous or toxic substance elements are expected to leak or deteriorate during normal use. Forty years is the expected useful life of the product.

ESD Sensitive Device

This symbol indicates the instrument is sensitive to electrostatic discharge (ESD). ESD can damage the highly sensitive components in your instrument. ESD damage is most likely to occur as the module is being installed or when cables are connected or disconnected. Protect the circuits from ESD damage by wearing a grounding strap that provides a high resistance path to ground. Alternatively, ground yourself to discharge any built-up static charge by touching the outer shell of any grounded instrument chassis before touching the port connectors.

This symbol denotes a hot surface. The side cover of the module will be hot after use and should be allowed to cool for several minutes.

Cleaning Precautions:

To prevent electrical shock, disconnect the Keysight Technologies instrument from mains before cleaning. Use a dry cloth or one slightly dampened with water to clean the external case parts. Do not attempt to clean internally. To clean the connectors, use alcohol in a well-ventilated area. Allow all residual alcohol moisture to evaporate, and the fumes to dissipate prior to energizing the instrument.

Definitions for specifications

Specifications describe the warranted performance of calibrated instruments that have been stored for a minimum of 2 hours within the operating temperature range of 0 to 45 °C, unless otherwise stated, and after a 45 minute warm-up period. Data represented in this document are not specifications unless otherwise noted.

Characteristics describe product performance that is useful in the application of the product, but that is not covered by the product warranty. Characteristics are often referred to as Typical or Nominal values.

  • Typical describes characteristic performance, which 80% of instruments will meet when operated over a 20 to 30 °C temperature range. Typical performance is not warranted.
  • Nominal describes representative performance that is useful in the application of the product when operated over a 20 to 30 °C temperature range. Nominal performance is not warranted.


Get More Assistance

  • Related Documentation
  • Go to Product Website
  • Go to Support Website


View Product Information on Keysight.com

To go to the Product Website, click on the following link:

http://www.keysight.com/find/digitizers


View Support Information on Keysight.com

To go to the Support Website, click the following link:

http://www.keysight.com/find/support


TIP: Help Search Tricks

In the help system, a basic search of topics consists of the word or phrase that you want to find. You can, however, improve your search results by using wildcard expressions, nested expressions, Boolean operators, and searching similar word matches, previous results, and topic titles only.

Performing a Basic Full-Text Search

  1. In the navigation pane, click the Search tab and then type the word or phrase that you want to find. Use the right-arrow button to add Boolean operators to your search.
  • Click List Topics.Your search will return the first 500 hits. If you want to sort the topic list, click Title, Location, or Rank.
  • Highlight the topic that you want, and then click Display You can also display any topic by double-clicking it.

Refining a Your Search

You can refine a basic search by using wildcard expressions, nested expressions, and Boolean operators. You can also search only on the previous results list, request similar word matches, or search only the titles of topics in the table of contents.

  • To refine a search to include just the last group of topics you searched, select the Search previous results check box.
  • To match similar spellings in a full-text search, select the Match similar words check box.

When Match similar words is selected, the viewer matches minor grammatical variations of the word or phrase you entered, as well as the word or phrase itself. For example, if you entered "test" and selected this box, the Library viewer would find "test", "tests", and "testing". This option is independent of other options or syntax. If you do a titles-only search, variations in titles will be matched. If you use quotes (or any other query operator) any variation of the word can appear; for example, "installed module" will also match "installing module".

  • To search for words in document titles only, select the Search titles only check box.

Search Syntax

The basic rules for formulating queries are as follows:

  • Searches are not case-sensitive, so you can type your search in uppercase or lowercase characters.
  • You can search for any combination of letters (a–z) and numbers (0–9). You cannot search for single letters (a, b, c, etc.) and the following reserved words: an, and, as, at, be, but, by, do, for, from, have, he, in, it, not, of, on, or, she, that, the, there, they, this, to, we, which, with, you.
  • Punctuation marks such as the period (.), colon (:), semicolon (;), comma (,), and hyphen (-) are ignored during a search.
  • Group the elements of your search using "double quotes" or (parentheses). You cannot search for quotation marks.
If you are searching for a filename with an extension, you should group the entire string in double quotes ("filename.ext"). Otherwise, the search will treat the period as an OR operator.

Words, Phrases, and Wildcards

You can search for words or phrases and use wildcard expressions. The table below describes the results of these different kinds of searches.

Search for | Example | Results
Single word | Calibrate | Topics that contain the word "calibrate." (You will also find its grammatical variations, such as "calibration" and"calibrated".)
Phrase | "saved configuration" -or- 'saved configuration' | Topics that contain the literal phrase "saved configuration" and all its grammatical variations. Without the quotation marks, the query is equivalent to specifying a saved AND configuration, which will find topics containing both of the individual words, instead of the phrase.
Wildcard expressions | Meas* | Topics that contain the terms "Meas," "measure," "measurement," and so on. The asterisk cannot be the only character in the words.
 | 89?00 | Topics that contain the terms "89500," "89600," "89700," and so on. The question mark cannot be the only character in the term.
 | *936* | Topics that contain the terms "936." "45936,""M9360A," "93600" and so on.
 | *93 | Topics that contain the terms "293," "393," "x93," "ABCD393," "8093," and so on.

Operators: AND, OR, NOT, and NEAR

The AND, OR, NOT, and NEAR operators allow you to refine your search. The following table shows how to use each of these operators.

Search for | Example | Results
Both terms in the same topic | performance AND verification -or- performance & verification | Topics containing both the words "performance" and "verification."
Either term in a topic | front OR panel -or- front | panel | Topics containing either the word "front" or the word "panel."
The first term without the second term | system NOT requirements -or_ system ! requirements | Topics containing the word "system," but not the word "requirements."
Both terms in the same topic, close together | install NEAR hardware | Topics containing the word "install" within eight words of the word "hardware."

Rules for Nested Expressions

The basic rules for searching topics using nested expressions are as follows:

  • You can use parentheses to nest expressions within a query. The expressions in parentheses are evaluated before the rest of the query.
  • If a query does not contain a nested expression, it is evaluateds from left to right. For example, "Instrument NOT system OR calibration" finds topics containing the term "instrument" without the term "system", or topics containing the term "instrument" and not "calibration". (On the other hand, "instrument NOT (system OR calibration)" finds topics containing the term "instrument" without either of the terms "system" or "calibration".)
  • Nesting allows you to create more complex search expressions. For example, "instrument AND ((system OR calibration) NEAR performance)" finds topics containing the term "instrument" along with the terms "system" and "performance" close together, or containing "instrument" along with the terms "calibration" and "performance" close together.
  • You cannot nest expressions more than five levels deep.


FAQs

Q. What is Coherent Sampling

A. Coherent Sampling refers to the relationship between the input frequency, sampling frequency, number of cycles in the sampled set and the number of samples. With coherent sampling one is assured that the signal power in an FFT is contained within one FFT bin (assuming a single input tone).

The condition for coherent sampling is given by:

For example if we have Msamples = 211, and fs = 100e6, and we expect and input frequency close to fs/2, let's say fin = 44 MHz, then Ncycles = 901.12 which is close to an integer. We could therefore round down to Ncycles = 901 and we would get fin = 43.994140625 Mhz, which is an input frequency that satisfies coherent sampling.

The integer number should be chosen carefully. We have three possible types of integers, even, odd, and prime. Even is not a good idea since we would hit the same code every Msamples, where M can be much less than N. Odd is a better idea since it takes longer to hit the same code. According to some sources a prime number of cycles is the best (with the exception of the prime 2) because it takes a long time before the same code repeats.


Related Documentation

Documentation Access Map

All documentation relating to your Keysight Technologies digitizer may be found either from the DVDs supplied with your product, or from the Keysight website as shown in the diagram below:

Documentation

If you have run the Keysight MD1 software installer for your product on your PC, the related product documentation will have been installed to your hard drive. Otherwise these documents are available for download from the Keysight Technologies website.

Document | Description
Startup Guide | Includes procedures to help you to unpack, inspect, install (software and hardware), perform instrument connections, verify operation, and troubleshoot your product. Also includes an annotated block diagram.
User Manual | Provides in-depth information and reference material specific to your digitizer product
Data Sheet | In addition to a detailed product introduction, the data sheet supplies full product specifications.
Soft Front Panel (help system) | Provides information on the use of the Soft Front Panel for MD1 digitizers.
LabVIEW Driver reference (help system) | Provides detailed documentation of the LabVIEW G driver API functions.
IVI Driver reference (help system) | Provides detailed documentation of the IVI-COM and IVI-C driver API functions, as well as information to help you get started with using the IVI drivers in your application development environment.


Full Product Family Listing & Cross-reference tables

This help file has been organized to allow easy access by arranging the product lines under their form factors listed below:

PCI Express Digitizers

The products in the industry standard PCI Express format benefit from the very high data transfer rates of the PCIe interface, and occupying a single slot in a host PC. They also feature programmable on-board processing capabilities.

Keysight Model Number | Model Name
U1084A | 8-bit High-Speed PCIe Digitizer with on-board signal processing
U5303A | 12-bit PCIe High-speed Digitizer with on-board signal processing
U5309A | 8-bit PCIe High-Speed Digitizers with on-board signal processing

Note: That the U1084A product utilizes PCIe Gen 1.1 and a x4 slot, whereas the U53xx series support PCIe Gen 2.0 and a x8 slot.

PXI Express High-Speed Digitizers

This product line is composed of Keysight PXI Express new generation of high-speed digitizers.

These are PXI Express compliant, using either a PXIe or PXIe Hybrid slot. Designed to benefit from fast data interfaces, the products can be integrated with other test and automation modules in PXIe and Hybrid chassis slots. The PXI format offers high performance in a small, rugged package. It is an ideal deployment platform for many automated test systems

Keysight Model Number | Model Name
M9202A | PXI Express 12-bit Wideband IF Digitizer
U5203A | PXI Express 12-bit High-Speed Digitizer
PXI Hybrid High-Speed Digitizers

This product line is composed of Keysight PXI Hybrid high-speed digitizers.

These are PXI compliant digitizers, using either a cPCI (J/J2), PXI-1 or PXIe Hybrid slot. The PXI format offers high performance in a small, rugged package. It is an ideal deployment platform for many automated test systems.

Keysight Model Number | Model Name
M9210A | 10-bit Digitizing Scope
M9211A | 10-bit UWB IF Digitizer
AXIe Digitizers

This product line is composed of Keysight Technologies new generation of AXIe Digitizers.

The AXIe format offers high performance in a highly scalable package, offering at least twice the channel density of currently available comparable solutions. Making it ideally suited to large scale experiments in applied physics, such as particle physics, nuclear fusion, hydrodynamics or microwave radio astronomy.

Keysight Model Number | Model Name
M9703A | AXIe 12-bit, 8-channels Wideband Digitizer
M9709A | AXIe 8-bit, 32-channels Wideband Digitizer


Keysight M9703A Introduction

The Keysight M9703A is a highly versatile DC-coupled 12-bit wide-band digital receiver/digitizer, providing exceptional measurement fidelity over multiple phase-coherent channels.

Based on the AXIe standard, and offering eight acquisition channels in a single-slot card, it provides excellent channel density and flexible scalability. These features allow the implementation of a large number of high dynamic range, phase-coherent channels in a small volume, making the M9703A ideal for multi-channel applications in advanced physics, aerospace & defense, or RF communications.

Example applications :

  • Advanced research fields, such as hydrodynamics or plasma fusion

  • Radar and satellite communication applications, such as antenna array calibration/test, passive radar receivers, or multi-band SATCOM monitoring

  • Emerging standards R&D and DVT in wide-band MIMO, or multichannel Base-band IQ

The simplified block diagram below shows the functional blocks of the M9703A:

Figure 1 - M9703A Block Diagram

Most of the technical specifications concerning your particular digitizer are covered in this manual, however for the complete specifications please refer to the product’s datasheet from the Keysight Technologies web site www.keysight.com/find/M9703A. These data sheets are available in pdf format and are best viewed using Adobe Acrobat software. If you have trouble accessing our web site, or viewing the data sheets, please contact your nearest sales office.


M9703A Front Panel Features

Front Panel Connectors

Connector | Type | Description
IN (1 - 8) | SMA female | The analog signal inputs, which are DC-coupled and 50 Ω terminated. The input full scale ranges are selectable, either 1 V or 2 V. Maximum signal level is ±5 V continuous. Frequency range is DC to 650 MHz (-F05) or DC to 1 GHz (-F10).
REF IN | MCX female | This external reference clock input is AC coupled and 50 Ω terminated. It can accept a 100 MHz signal up to 3 dBm Collapsed Power measurement relative to 1 mW, P (dBm) = 10log10(1000.P) (0.3 V rms / 50 Ω).
CLK IN | SMA female | This external clock source is AC-coupled, with 50 Ω termination, and can accept signals up to +15 dBm Collapsed Power measurement relative to 1 mW, P (dBm) = 10log10(1000.P) (1.26 V rms / 50 Ω). Frequency : 1 GS/s option (-SR1) = 2 GHz, and for 1.6 GS/s option (-SR2) = 2 to 3.2 GHz.
TRG 1, 2, 3 | MCX female | These external trigger inputs are DC-coupled, 50 Ω terminated. The trigger level range is ±5 V.
TRG OUT | MCX female | Trigger Out signal. User selectable from several functions.
DPU Collapsed Digital Processing Unit JTAG | USB Mini | JTAG FPGA Collapsed Field Programmable Gate Array debugging interface. Used in conjunction with the U5340A FDK Collapsed FPGA Development Kit.
CTR JTAG | USB Mini | Not currently supported.
I/O 1, 2 | MCX female | User configurable Input / Output signal. 3.3 V CMOS and TTL compatible.

Front Panel LEDs

Indicator | Purpose | Color | State | Meaning
H/S | Hot Swap |  | Off | Normal operating mode
 |  |  | Blue, blinking | Initializing
OOS | Out Of Service |  | Off | ATCA bus is ready
 |  |  | Red | ATCA bus is not ready
LA, LB, LC, LD | DPU Collapsed Digital Processing Unit status |  | Off | DPU Collapsed Digital Processing Unit FPGA Collapsed Field Programmable Gate Array is not configured
 |  |  | White | Idle
STATUS | Instrument status |  | White, blinking | Firmware initialization in progress
 |  |  | Green, blinking | Software initialization in progress
 |  |  | Yellow, blinking | Warning (see note below)
 |  |  | Red, blinking | Error (see note below)
 |  |  | Green | OK

If warning or error status is observed, please try the following steps:

  • Power-cycle the chassis (If using a PCIe interface to external PC, observe the power sequence requirements)
  • If the error persists please contact Keysight technical support http://www.keysight.com/find/assist.


Channel Input Specifications

This section provides information and specifications regarding the input characteristics of the digitizer.

The M9703A provides eight 1.6 GS/s 12-bit DC-coupled channels distributed on 4 front-end mezzanines. The two channels of each mezzanine may be combined to form an interleaved channel at 3.2GS/s (M9703A-INT option).

The M9703A-FRF provides optimized analog performance providing very high measurement integrity.

Channel Input

The M9703A has the following front end capabilities:

Coupling / Impedance | Full Scale Ranges (FSR Collapsed Full Scale Range:- The span of the voltage input of the Digitizer (negative to positive) including the configured offset voltages.) | Maximum input voltage | Offset Adjustment
DC / 50 Ω | 1 V | 3 V RMS, ± 3.6 Vpk | ±2 x FSR Collapsed Full Scale Range:- The span of the voltage input of the Digitizer (negative to positive) including the configured offset voltages.
 | 2 V | 4.3 V RMS, ± 6.3 Vpk | ±2 x FSR Collapsed Full Scale Range:- The span of the voltage input of the Digitizer (negative to positive) including the configured offset voltages.

Impedance & Coupling

The input channel termination is 50 Ω. The input coupling is DC.

Input Protection

The input amplifiers are designed to accept signals below the level shown in the table.

Mezzanine Front-end

The front-end electronics are all mounted on a removable mezzanine card. In the event of accidental damage or as components fatigue over time (e.g. relays in high duty cycle automated testing applications), the mezzanine card allows for fast and efficient replacement.

Bandwidth and Rise Time

The bandwidth specification indicates the frequency at which an input signal will be attenuated by 3 dB (approximately 30% loss of amplitude).

Options |  |  | Input Frequency Range |  | BW Limiter selections
 |  |  | 1 V FSR Collapsed Full Scale Range:- The span of the voltage input of the Digitizer (negative to positive) including the configured offset voltages. | 2 V FSR Collapsed Full Scale Range:- The span of the voltage input of the Digitizer (negative to positive) including the configured offset voltages.
-F05 | -SR1/-SR2 | — | DC to 650 MHz (typical) |  | -
 |  | -INT
-F10 | -SR1/-SR2 | — | DC to 1.9 GHz (typical) | DC to 2.0 GHz (typical) | 650 MHz
 |  | -INT | DC to 1.4 GHz (typical)

The bandwidth also affects the minimum rise and fall times that can be passed through the front-end electronics. A pulse with a very sharp edge will be observed to have a minimum rise time Tmin determined by the front-end electronics. In general a pulse with a given 10-90% rise time T10-90real will be observed with a slower value given by:

Vertical Resolution

The M9703A AXIe High-Speed Digitizer uses a 12-bit ADC Collapsed Analog to Digital Converter giving 4096 levels of ~0.25 mV average width when using the 1 V FSR Collapsed Full Scale Range:- The span of the voltage input of the Digitizer (negative to positive) including the configured offset voltages.. The effective number of bits (ENOB Collapsed Effective Number Of Bits - expresses the quality of the ADC quantification.) is greater than 9 (typical) over the full -F05 bandwidth (M9703A-FRF).

Accuracy and Linearity

This digitizer uses low noise front-end electronics in order to ensure that voltage measurement is made with accuracy and precision. DC accuracy is typically 1%. DC gain accuracy is better than ±0.5 % in the 1 V range, and ±0.7 % in the 2 V range. Offset accuracy is better than ±0.5 % in the 1 V range, and ±1.5 % in the 2 V range.


Data Acquisition

The table below summarizes the data acquisition characteristics, and further discussed in the sections that follow:

Model | Max. Sampling Rate [GS/s] | Max Converters per Channel / Channels | Memory / Samples per channel | Maximum Segments
M9703A (default options -F05-SR1-M10) | 1 | 2 / 8 | 1 GB 64 MS/ch | 65536
M9703A-SR2 (option) | 1.6 | 2 / 8 | -
M9703A-M10 (option) | - | - | 1 GB 64 MS/ch
M9703A-M40 (option) | - | - | 4 GB 256 MS/ch
M9703A-M16 (option) | - | - | 16 GB 1 GS/ch

Note: That more than one option may be applied e.g. M9703A-M20- SR2 will have 2 GB memory and 1.6 GS/s sampling rate.

Sampling Rate

When using the internal clock the M9703A Digitizer samples waveforms at either 1 or 1.6 GS/s depending on the option purchased. If purchased with the -INT option, this further allows two channels to be interleaved, providing sampling rates of 3.2 GS/s. Optionally an external clock input 'CLK IN' may be used. See "External Clock and Reference"

Combining channels (Interleaving -INT option)

By default the M9703A provides a Sample Rate of 1 GS/s per channel (M9703A-SR1) or 1.6 GS/s per channel (-SR2) that may be interleaved in to give sampling rates of 2 GS/s or 3.2 GS/s respectively. (Note, interleaving requires the -INT option). This channel combination is only possible between channel pairs - 1/2, 3/4, 5/6 or 7/8.

Acquisition Memory

Data from the ADC Collapsed Analog to Digital Converter is stored in on-board acquisition memory. The amount of memory in use for acquisition can be programmed and is selectable from 1 point to the full amount of acquisition memory available.

For technical reasons, a certain acquisition memory “overhead” is required for each waveform, reducing the available memory by a small amount. To ensure maximum sampling rate and high timing resolution, we strongly recommend the use of long acquisition memories whenever possible.

After acquisition, the raw 12-bit data is subjected to post-calibration processing, which compensates for gain and offset errors in the internal ADCs, The result of this post-processing is then stored and read-out as a 16-bit value. For this reason the returned data will not always be divisible by 16 as may be expected.

Single Acquisition Mode

Digitizers acquire waveforms in association with triggers. Each waveform is made of a series of measured voltage values (sample points) that are made by the ADC Collapsed Analog to Digital Converter at a uniform clock rate.

Sequence Acquisition Mode

The digitizers also feature a Sequence Acquisition mode. This allows the capture and storage of consecutive “single” waveforms. Sequence Acquisition mode is useful as it can optimize the digitizers sampling rate and memory requirements for applications where only portions of the signal being analyzed are important. The mode is extremely useful in almost all impulse-response type applications (RADAR, SONAR, LIDAR, Time-of-Flight, Ultrasonics, Medical and Biomedical Research, etc.).

In the API, the term 'MultiRecord' is used for 'Sequence' and 'Record; is used for 'Segment'.

In Sequence Acquisition mode the acquisition memory is divided into a pre-selected number of segments. Waveforms are stored in successive memory segments as they arrive. Each waveform requires its own individual trigger.

Sequence acquisition enables successive events, which can occur within a very short time, to be captured and stored without loss. A crucial feature of Sequence Acquisition mode is that it has a very fast trigger rearm time. A fast trigger rearm helps produce very low “dead time” between the segments of a sequence acquisition. The “dead time” is the period after the end of an event when the card cannot digitize data for a new trigger event.

Trigger Time Interpolator

The digitizer also measures and stores the arrival time of each trigger using the information from the on board Trigger Time Interpolator (TTI Collapsed Trigger Time Interpolator:- A function that accurately measures the time from the trigger point to the first sample point. The TTI permits accurate positioning of the trigger signal with respect to the internal clock (sampling time).). This information is essential for determining the precise relation between the trigger and the digitized samples of the signal. The TTI Collapsed Trigger Time Interpolator:- A function that accurately measures the time from the trigger point to the first sample point. The TTI permits accurate positioning of the trigger signal with respect to the internal clock (sampling time). resolution determines the resolution of the trigger time stamps.

Timebase Range

The timebase range defines the time period over which data is being acquired. For example, the M9703A has a standard acquisition memory of 64 Mpoints (per channel) and sampling rate of 1 GS/s. Therefore, at the maximum sampling rate, the digitizer can record a signal over a timebase range of up to 65 ms (approx. 65,000,000 points * 1 ns/point). The timebase range can be adjusted by varying the amount of acquisition used.

This may be optionally upgraded to 256 Mpoints, and 1.6 GS/s with the respective options.

Binary Decimation

A programmable binary decimation may be used to lower the sample rate by a factor of 2n where n is in the range of 1 to 5.

e.g. for a M9703A-SR2 you can select from 3.2 GS/s down to 100 MS/s.


Trigger

The trigger settings applied to the digitizer are used to determine at which time the device will stop acquiring data. The various trigger settings are outlined below.

Trigger Source

The trigger source can be a signal applied to one of the External Trigger Inputs. These inputs provide fully functional trigger circuits with selectable level and slope. The external trigger circuit has diode protection against overload. A ±5 V limit on trigger signals should be respected, although somewhat higher voltages for short time periods will not damage the unit.

Possible trigger sources for the M9703A are:

Trigger Source | Front panel label | Description
Channel 1- 8 | IN 1 - 8 | Any one of the eight input channels may be used as the trigger source .
External 1 - 3 | TRG 1 - 3 | Any one of the three external trigger inputs may be used as the trigger source (MCX connector).
AXIe SYNC | - | The AXIe SYNC line may also be used as the trigger source.

Trigger Impedance & Coupling

The M9703A has a fixed 50 Ω termination impedance with DC coupling.

Trigger Input Bandwidths

The bandwidth of the channel triggers is from DC to 250 MHz.

The external trigger inputs have a bandwidth of DC to 2 GHz.

Trigger Level

The trigger level specifies the voltage at which the selected trigger source will produce a valid trigger. All trigger circuits have sensitivity levels that must be exceeded in order for reliable triggering to occur.

Both the external trigger input and channel triggers have a hysteresis of 5% of FSR Collapsed Full Scale Range:- The span of the voltage input of the Digitizer (negative to positive) including the configured offset voltages. (Full Scale Range).

On external trigger, the Full Scale Range FSR Collapsed Full Scale Range:- The span of the voltage input of the Digitizer (negative to positive) including the configured offset voltages. is ±5 V, therefore the digitizer will trigger on signals with a peak-to-peak amplitude > 0.5 V.

When using the channel triggers, the trigger level must be set within Offset ± FSR Collapsed Full Scale Range:- The span of the voltage input of the Digitizer (negative to positive) including the configured offset voltages. (where FSR Collapsed Full Scale Range:- The span of the voltage input of the Digitizer (negative to positive) including the configured offset voltages. is the channel Full Scale Range).

Edge Trigger Slope

The trigger slope defines which one of the two possible transitions will be used to initiate the trigger when it passes through the specified trigger level. Positive slope indicates that the signal is transitioning from a lower voltage to a higher voltage. Negative slope indicates the signal is transitioning from a higher voltage to a lower voltage.

Trigger Time Interpolator

The digitizer also measures and stores the arrival time of each trigger using the information from the on board Trigger Time Interpolator (TTI Collapsed Trigger Time Interpolator:- A function that accurately measures the time from the trigger point to the first sample point. The TTI permits accurate positioning of the trigger signal with respect to the internal clock (sampling time).). This information is essential for determining the precise relation between the trigger and the digitized samples of the signal. The TTI Collapsed Trigger Time Interpolator:- A function that accurately measures the time from the trigger point to the first sample point. The TTI permits accurate positioning of the trigger signal with respect to the internal clock (sampling time). resolution determines the resolution of the trigger time stamps.

Please refer to the M9703A datasheet for the relevant specifications.

Trigger precision and resolution

Pre- and Post-Trigger Delay

To increase trigger flexibility a pre- or post-trigger delay can be applied to the trigger position.

The amount of pre-trigger delay can be adjusted between 0 and 100% of the acquisition time window (i.e. sampling interval x number of samples), whereas the post-trigger delay can be adjusted within the time interval

from 0 to (232 – 1) * block_size (samples)

where block_size is 16.

Pre- or post-trigger delays are just different aspects of the same trigger positioning parameter:

  • The condition of 100% pre-trigger indicates that all data points are acquired prior to the trigger, i.e. the trigger point is at the end of the acquired waveform.
  • The condition of 0% pre-trigger (which is identical to a post-trigger of 0%) indicates that all data points are acquired immediately after the trigger, i.e. the trigger point is at the beginning of the acquired waveform.
  • The condition of a non-zero post-trigger delay indicates that the data points are acquired after the trigger occurs, at a time that corresponds to the post-trigger delay, i.e. the trigger point is before the acquired waveform.

The digitizer hardware accepts pre- and post-trigger adjustments in increments of 16 samples. By definition post-trigger settings are a positive number and pre-trigger settings are a negative number.

Thus it is only natural that the software drivers treat pre- and post-trigger delays as a single parameter in seconds that can vary between

– NbrSamples * SamplingInterval (100% pre-trigger)

and +maxPostTrigSamples * SamplingInterval (max post-trigger).


External Clock and Reference

For applications where the user wants to replace the internal clock of the digitizer and drive the ADC Collapsed Analog to Digital Converter with an external source, either an External Clock, External Reference or the AXIe Reference signal can be used.

External Clock (CLK IN)

The External Clock may be used to vary the sampling rate of the digitizer, it must be continuously present if selected for the digitizer to operate correctly. The input is AC coupled.

Parameter | Value
Frequency Range
SR1 | 1.8 to 2 GHz
SR2 | 2 to 3.2 GHz
Minimum Amplitude | 0.5 Vp.p into 50 Ω
Maximum Power | 15 dBm Collapsed Power measurement relative to 1 mW, P (dBm) = 10log10(1000.P)
Maximum Voltage | ±10 V
Threshold | 0 V

Since the clock is divided by two internally, the frequency range of 1.8 GHz to 3.2 GHz corresponds to sample rates from 900 MS/s to 1.6 GS/s.

For example, in 8-channel (uncombined) mode, an external clock input of 1.8 GHz will correspond to a sampling rate of 900 MS/s per channel. If the digitizer is used in 4-channel (interleaved) mode the sampling rate will be doubled and 1.8 GS/s per channel will be achieved with the same 1.8 GHz external clock.

External Reference (REF IN)

For applications that require greater timing precision and long-term stability than is obtainable from the internal clock, a 100 MHz Reference signal can be used. The External Reference is nominally at 100 MHz. However, frequencies in a range will be accepted.

If your input is not at exactly 100 MHz, you must remember to compensate for the difference in your application since the digitizer and the driver have no way to know about such deviations.

Parameter | Value | Tolerance
Nominal Frequency | 100 MHz | ±5 kHz
Minimum Amplitude | 0.5 Vp.p into 50 Ω |
Maximum Power | 3 dBm Collapsed Power measurement relative to 1 mW, P (dBm) = 10log10(1000.P) |
Maximum Voltage | ±10 Vdc |

If synchronization between several digitizers is required, the reference signal should be applied to all of them.

AXIe Reference

This 100 MHz signal is provided via the AXIe backplane to the M9703A digitizer and may be selected as a reference clock.

This AXIe Reference may also be optionally locked to an external 10 MHz input applied to the 'CLOCK IN' connector of the AXIe chassis. To implement this the 10 MHz signal must be present before the chassis is powered-up, and when detected the chassis will automatically lock the AXIe Reference to this signal.


Internal Calibration and Factory Calibration

Internal Calibration

The digitizer includes a high precision voltage source and a 16-bit DAC, used to perform the input voltage and offset calibration.

The software drivers supplied include calibration functions for the timing, gain and offset parameters, which can be executed upon user request. The digitizers are never calibrated in an “automatic” way, (i.e. as a side effect of another operation). This ensures programmers have full control of all calibration operations performed through software in order to maintain proper event synchronization within automated test applications.

For accurate time and voltage measurements it is recommended to perform a calibration once the module has attained a stable operating temperature (usually reached with a few minutes of digitizer operation after power on). And subsequently a self-calibration should be carried out after any configuration changes are made to the digitizer, before making acquisitions.

A full internal calibration of a digitizer can be time consuming. Therefore, several other options are available. They are documented in the calibration routines associated with the API. A program can always be started with the digitizer in an un-calibrated state and recorded data can be used for many kinds of testing. However, as soon as accurate data compliant with the specifications of the instrument are required, a calibration of the current acquisition state is mandatory.

The full internal calibration has the advantage that it generates the calibration constants needed for any possible configuration of the instrument; its disadvantage is the time taken. If a more selective calibration is done it will allow the generation of good data in the current acquisition state. This calibration will remain useable whenever that acquisition state is used again for as long as the temperature of the instrument does not change significantly. A fast calibration of a channel in a configuration can be done in around a 5 seconds. Many applications can save time by only performing calibration for the configurations that will actually be used.

Calibration can usually be performed with signals present at the channel, external, and clock inputs. However, to ensure the best performance, or if the calibration is found to be unreliable, as shown by a calibration failure status, it will be necessary to remove such signals.

An application program will shut-down devices at exit. As a consequence, an appropriate warm-up period is expected when starting another application program. In this case, it is recommended to wait for couple of minutes for a stable device temperature, before launching the calibration to ensure full performance.

Factory Calibration

Whilst the Internal Calibration function will provide a good degree of confidence that your instrument is operating within its specifications on a day-to-day basis, Keysight Technologies recommends that each instrument undergoes a Factory Calibration at least annually to ensure that it remains within the specified performances.

Factory Calibration is the process of measuring the actual performance of an instrument-under-test using lab instruments that in turn have significantly better performance than the instrument-under-test. Lab instrument performance must be traceable to the International System (SI) Units via a national metrology institute (NIST, NPL, NRC, PTB, CENAM, INMETRO, BIPM, etc.)

The measured performance is then compared to published datasheet specifications. For each factory calibration, Keysight Technologies tests the performance corresponding to all datasheet specifications, for every installed option. If needed, the instrument is adjusted and re-qualified before returning it to be in line with full specifications.

For more information, or to request for a calibration please see www.keysight.com/find/calibration.


Trigger Output

When the digitizer is ready to be triggered and a valid trigger signal occurs, a trigger output pulse is generated for external use. This signal is available on the front panel TRG OUT MCX connector, and may be enabled or disabled as required.

There are several trigger sources which may be assigned to the Trigger Out connector, but the available options will depend on the model being used.

Trigger Out Sources | Description of signal
(0) No Sync | A pulse signal is sent directly to the Trigger Out. This signal is active low. The pulse width is ~300 ns typically.
(1) Sync | A pulse signal resynchronized to the sample clock is sent to the Trigger Out. This signal is active low. The pulse width is ~300 ns typically.
(3) Trig compare | The trigger input condition has been satisfied, but not necessarily triggered e.g the trigger enable was not asserted. The signal is active low.
(4-15) AXIe TRIG <n> | The AXIe bussed trigger signal TRIG <n>
(16) AXIe STRIG | The AXIe Star Trigger (STRIG) is sent to the Trigger Out.
(17) High Level | Fixed 'high' level signal for debug purposes.
(18) Low Level | Fixed 'low' level signal for debug purposes.

Figure 2 - Trigger Output Block diagram:

In the default software configuration, the output swing is 1.6 V (±0.8 V) when unloaded and 0.8 V (±0.4 V) when terminated on 50 Ω. The rise and fall times are 2.5 ns typical. The offset can be adjusted, by software control in the range [–2.5 V to +2.5 V] unloaded, or [-1.25 V to +1.25 V] into 50 Ω. The maximum output current capability is ±15 mA. As the output is retro-terminated, it is possible to drive a 50 Ω line un-terminated (HiZ) without loss of performance.

For a TTL compatible signal, set the offset to 1.0 V and the swing at destination will be +0.2 to +1.8 V.

For an ECL compatible signal, terminated on 50 Ω to –1.2 V, set the offset to –1.2 V and the output will be in the range [–0.8 to –1.6 V]).

Alternatively, to reduce the current drawn from the digitizer, the terminations shown here can be used:

Figure 3 - Suggested trigger signal terminations

The External Trigger Output functionality is implemented in the hardware. No Trigger Out signal occurs for software-generated triggers.


Multi-Purpose Inputs and Outputs

The IO connectors may be used for any of the functions shown in the following table:

IO Connector Functions | Type | Description of signal | Notes
Inputs
Disabled | - | IO connector is disabled. |
In-ToLogicDevices | - | The Pio_In input signal to the DPU Collapsed Digital Processing Unit user core (see U5340A FDK Collapsed FPGA Development Kit manual user core signal description) IO 1: Pio_In(0), IO 2: Pio_In(1) These signals are resynchronized to the sampling clock divided by 16 and transferred from the Control FPGA Collapsed Field Programmable Gate Array to the DPU Collapsed Digital Processing Unit with a non-deterministic clock cycle latency. | Used only with the U5340A FPGA Collapsed Field Programmable Gate Array Development Kit.
Outputs |  |  |
Out-LogicDeviceDPUA Out-LogicDeviceDPUB Out-LogicDeviceDPUC Out-LogicDeviceDPUD | - | The Pio_Out output signal from the DPU Collapsed Digital Processing Unit user core (see U5340A FDK Collapsed FPGA Development Kit user manual, user core signal description) IO 1: Pio_Out(0) IO 2: Pio_Out(1) These signals are transferred from the DPU Collapsed Digital Processing Unit to the Control FPGA Collapsed Field Programmable Gate Array with a non-deterministic clock cycle latency. | Used only with the U5340A FPGA Collapsed Field Programmable Gate Array Development Kit.
Out-UserSync | Pulse | The SyncOut output signal from the DPU Collapsed Digital Processing Unit user core (see U5340A FDK Collapsed FPGA Development Kit user manual, core signal description) This signal is transferred from the DPU Collapsed Digital Processing Unit to the Control FPGA Collapsed Field Programmable Gate Array with a deterministic clock cycle latency. | Used only with the U5340A FPGA Collapsed Field Programmable Gate Array Development Kit.
Out-AcquisitionActive | Level | Indicates that the acquisition is currently running. |
Out-Trigger Armed | Level | Active when the instrument is armed and waiting for a valid trigger event. |
Out-Low Level | Level | Fixed 'low' level signal for debug purposes. |
Out-High Level | Level | Fixed 'high' level signal for debug purposes. |
Out-Trigger Accepted Resync | Pulse | Active when a valid trigger event has occurred. This signal is resynchronized to the sample clock. |

Signal Logic Levels

The multi-purpose IO signals are 3.3 V CMOS compatible. The levels shown in the table below should be observed.

Direction | Low level | High level
Input | <0.8 V | >2.0 to 3.45 V
Output | In the range 0 to 0.8 V | In the range 1.6 to 3.3 V
As an Input

An unconnected input will be pulled low via a 50 Ω internal termination.

As an Output

The high level output will typically give 0.8 V into 50 Ω. As can be seen in the diagram below, the 3.3 V output buffer has a 50 Ω resistor in series. Therefore the available output high level voltage will depend on the load applied. In the example below a 50 Ω termination will result in a nominal high level of 1.6 V. (Vo = Rload/50 + Rload * 3.3)

Figure 4 - Output equivalent circuit


Delay Controls

Introduction

Most Keysight modular digitizers incorporate as part of the internal calibration feature, the ability to automatically measure and adjust certain key timing parameters to obtain optimum performance. The M9703A additionally allows the user to manually set certain of these parameters to tune the signal path delays to suit a specific application or measurement.

This delay tuning feature is particularly useful for applications where the signal path timing is very important, or in developing a system calibration that includes signal path delay compensation.

Figure 5 - M9703A diagram showing clock distribution and delay controls

The delay control capability is disabled by default. Programming any of the delay values will override the calibration settings and neither the channel to channel skew specification nor any analog performances are warranted in such a mode.

Clock Distribution Control (CDC)

Provides a coarse control of the AXIe Reference Clock phase. This control accepts integer values from -7 to +7, the resulting phase advance/retard values are shown in the table below. Note that the function is not linear.

Input Value | Phase Advance/Retard
0 | 0
±1 | ±160 ps
±2 | ±320 ps
±3 | ±480 ps
±4 | ±830 ps
±5 | ±1130 ps
±6 | ±1450 ps
±7 | ±1750 ps

If finer control is required, consider using the AXIe Clock Phase control described below.

AXIe Clock Phase

The AXIe clock phase control provides a fine tuning control of the AXIe reference clock. It accepts an integer value from 0 to 4095, but it is recommended to remain within the linear region which extends to around 2048. This control and the CDC may be used together as a fine/coarse control method.

The relationship between the commanded value for delay and the actual delay will be temperature dependent and as such should be tuned for the situation in which it is required. However for reference, the curve shown in the diagram below is typical.

Figure 6 - M9703A AXIe Reference Delay Control typical curve

Sample Clock Distribution

The Sample Clock Distribution provides discrete control of the clocks applied to each of the four input mezzanines (channel pairs) and thus allows de-skewing to be performed between channel pairs (1/2, 3/4, 5/6 & 7/8).

This control has two ranges (high/low) which may be selected by the AgMD1DelayControlRangeEnum.

In normal operation these sample clock delays are automatically calibrated by the instruments self-calibration routine. However once the delay control function is enabled, these values will be overridden with default values (2048).

ADC Aperture Delay

The ADC Collapsed Analog to Digital Converter aperture delay control allows access to the ADC Collapsed Analog to Digital Converter of each mezzanine. Each ADC Collapsed Analog to Digital Converter has two registers:

  • Coarse delay control : 0 to 825 ps (±95 ps) in steps of 340 fs
  • Fine delay control : 0 to 2.3 ps (±0.3 ps) in steps of 36 fs

Figure 7 - M9703A ADC Collapsed Analog to Digital Converter Aperture Coarse Control register

Figure 8 - M9703A ADC Collapsed Analog to Digital Converter Aperture Coarse Control register

Programming the Delay Controls

For detailed reference material on the functions for programmers please refer to the MD1 IVI Help.

To summarize the controls which apply to the delay adjustment:

Delay control | Control name | Default value
Clock distribution control | DelayPLLReference | The internal 100 MHz reference is locked to the selected reference, zero additional delay.
AXIe clock phase | DelayAXIe100 | Locked to AXIe 100 MHz reference, zero additional delay.
Sample clock distribution | DelaySampleClockA DelaySampleClockB DelaySampleClockC DelaySampleClockD | Automatically calibrated
ADC Collapsed Analog to Digital Converter aperture delay | DelayCoarseADCA DelayFineADCA DelayCoarseADCB DelayFineADCB DelayCoarseADCC DelayFineADCC DelayCoarseADCD DelayFineADCD |

Functions:

AgMD1 _GetDelayControlName Returns the delay control name for a given index.

Attributes:

AGMD1_ATTR_DELAY_CONTROL_COUNT | The number of delay controls
AGMD1_ATTR_DELAY_CONTROL_ENABLED | Specifies whether the delay controls are set manually. If set to true, all delay controls must be set manually. When false, the delay controls are set by the self-calibration.
AGMD1_ATTR_DELAY_CONTROL_MAX | Maximum value (DAC code) that can be set for the delay control.
AGMD1_ATTR_DELAY_CONTROL_MIN | The Minimum value (DAC code) that can be set for the delay control.
AGMD1_ATTR_DELAY_CONTROL_VALUE | The value (DAC code) set for the delay control.


Signal Processing Options

This section describes options which may be used when processing the signal.

The following table show the availability of firmware options versus sampling rate.

Digital Down-Conversion Mode (DDC / LDC)

Custom Firmware (FDK)


Digital Down-Conversion mode (-DDC and -LDC)

This function is only available on the M9703A AXIe Digitizer with the -DDC option or the -LDC option.

Principle of operation

The Digital Down Converter (DDC) mode of the digitizer allows for operation as the Intermediate Frequency (IF) digitization element in a digital receiver. The M9703A offers 8 independent channels of down-conversion, each channel accepting data at rates up to 1.6 Gs/s and down converts the data to lower rates at arbitrary center frequencies.

Figure 1. Digital Down Conversion functional block diagram

Digital down conversion algorithms within the digitizer allow for the translation of the digitized IF to a complex-valued (I/Q) baseband output allowing analysis of narrowband signals. Filtering can be invoked to increase precision at reduced bandwidth and sample rates.

For example, say that one wished to capture a narrow band radio signal with a 1 Hz resolution on the sidebands. This would require capturing 1 second of data. Now, at the sample rate of the M9703A (1.6 GS/s) this would require massive amounts of memory, and an very large FFT. However, by using the DDC function and reducing the sample rate to say 1.56 MS/s you would only need to acquire 1/1000th of the data, making the measurement possible, and providing a much more reasonably sized FFT.

Reducing the bandwidth with a corresponding decrease in sample rate is a fundamental function of DDC. When the bandwidth of the ADC Collapsed Analog to Digital Converter data is reduced, both quantization noise and unwanted signals are removed from the sample stream. The effect of reducing bandwidth also increases the effective number of bits (ENOB Collapsed Effective Number Of Bits - expresses the quality of the ADC quantification.). The design ensures that the ENOB Collapsed Effective Number Of Bits - expresses the quality of the ADC quantification. at the minimum decimated bandwidth is sufficient to capture all data.

The decimation filters are state-synchronized across all channels, this maintains a time alignment across channels as well as ensuring a common LO phase across all DDCs. This synchronization is maintained even across all channels which are located on modules in the same chassis (2 or 5 slot).

Anti-aliasing

In order to eliminate the chance of aliasing, it is recommended to reduce the input signal bandwidth with low-pass filter at the input. This filter would generally be at fs/2, in the case of the M9703A that is 500 or 800 MHz depending on the option. More specifically, a filter with passband (A)fs and stopband (1-A)fs, with A typically being 0.4, which would provide an alias protected bandwidth of A*fs.Of course this may not be necessary where the input signal is already narrow-band. Signal conditioning should also scale the signal peak to close to the full-scale value (within 2dBm) at the digitizer input for optimum performance.

Re-arm Time

The re-arm time is defined as the time required after the completion of a data acquisition segment and before a new triggered acquisition segment can be accepted. The re-arm time for the DDC firmware is about 2 us across the entire selectable DDC bandwidth.

The following picture illustrates graphically the re-arm time concept. Each triggered acquisition lasts for a given amount of samples. Only after the re-arm time has completed, can a new trigger can be accepted and a new segment acquired.

Figure 9 - DDC Re-arm Time

Local Oscillator (Center Frequency)

Digital Down Conversion (DDC) is performed at an IF center frequency which is configurable by the user across the entire bandwidth of the digitizer, and with a resolution of 0.01 Hz, providing very flexible tuning capabilities. Note, that if the BW limiter is selected, the LO frequency should not be placed above 650 MHz. Similarly on the -F05 option model, setting the LO frequency above the maximum analog bandwidth of 650 MHz is not permitted.

Sampling Frequency & Bandwidth

Several model options effect the available sampling rate and bandwidth when in DDC mode. Firstly the sampling rate option(-SR1 or -SR2) of your M9703A, and also the DDC option which has been purchased. There is a full performance DDC option (-DDC) as well as a more cost-effective limited DDC option (-LDC).

In DDC mode the sampling frequency control also controls the bandwidth. These rates differ depending on the model option, and are shown in the table below. Note that the intermediate steps can be calculated using the formulas shown in the penultimate row.

 | Decimated Sampling Rate [MS/s] |  |  |  | Analysis Bandwidth [MHz] |  |  |  | Maximum Acquisition Memory Time [s]
 | -SR1 model |  | -SR2 model |  | -SR1 model |  | -SR2 model |  | -SR1 model |  | -SR2 model
n | -LDC | -DDC | -LDC | -DDC | -LDC | -DDC | -LDC | -DDC | -LDC | -DDC | -LDC | -DDC
0 | - | 250 | - | 400 | - | 180 | - | 300 | - | 2.147 | - | 1.342
1 | - | 125 | - | 200 | - | 100 | - | 160 | - | 2.147 | - | 1.342
2 | 62.5 |  | 100 |  | 50 |  | 80 |  | 4.294 |  | 2.684
3 | 31.25 |  | 50 |  | 25 |  | 40 |  | 8.589 |  | 5.368
4 | 15.625 |  | 25 |  | 12.5 |  | 20 |  | 17.179 |  | 10.736
5 | 7.812 |  | 12.5 |  | 6.25 |  | 10 |  | 34.359 |  | 21.472
6 | 3.906 |  | 6.5 |  | 3.125 |  | 2 |  | 68.719 |  | 42.949
... | (62.5/2n-2)* |  | (100/2n-2)* |  | (50/2n-2)* |  | (80/2n-2)* |  | 68.719 |  | 42.949
17 | 0.190 kS/s |  | 0.305 kS/s |  | 0.152 kHz |  | 244 kHz |  | 68.719 |  | 42.949

* with n>=2.

The results presented in this table are achieved with the -M16 option.

The top sample rate (400/250 MS/s) requires some special consideration. There are in fact two bandwidths to consider, the first being at 200/125 MHz (Half of sampling frequency i.e. Fs/2 or Nyquist rate), the second being at 120/75 MHz is the alias protected bandwidth, which is guaranteed free from alias products. For example if you know that your input signal is <= 200 MHz it will be safe to assume that the output does not contain alias products, however if the signal bandwidth is above 200 MHz or unknown you may consider signals from DC to 120 MHz as being free from alias products, but in the range 120 to 200 MHz these may be legitimate signals or may be aliases of higher frequency signals.

The difference between -DDC option and -LDC option is the maximum analysis bandwidth.

  • The -LDC option provides up to 80 MHz of real-time frequency span (analysis bandwidth) per channel (with -SR2 option).
  • The -DDC option provides up to 300 MHz of real-time frequency span (analysis bandwidth) per channel (with -SR2 option).

Data Scaling

In normal DDC operation it is required that, signal bandwidth around center frequency i.e. Fc ± BW/2 does not cross either 0 or the Nyquist frequency Fs/2 , and thus in processing the signal the negative spectrum component is filtered out by the down-converter. Therefore due to this filtering process the power level of the signal brought into baseband represents only half of the original (pre-DDC) signal power. To correct this a 'Data scaling' option is available, whereby a factor of two is applied to the amplitude, and the down-converted signal is returned to the true input power level. When is used, the user is operating with the same convention as 89600 VSA Software. Note that if the center frequency (Fc) is set to '0', this factor is not applied.

Data Readout

In order to optimize data transfers at the top sampling rate, a different data type is used compared to the lower sampling rates. The following applies:

  • Read, Fetch or FetchMulti methods in Real64 are supported for all sample rates.
  • Read, Fetch or FetchMulti methods in Int16 are supported for the highest sample rate only.
  • Read, Fetch or FetchMulti methods in Int32 are supported for all except the highest sample rate.

For these methods, the parameter ActualPoints is given in number of I-Q data point pairs, or complex samples. For the FetchMulti methods, the units of the OffsetWithinRecord and NumPointsPerRecord parameters are also complex samples. The FirstValidPoint parameter, which is primarily intended for dealing with memory alignment, is always given in array elements, like the WaveformArraySize parameter.

Trigger

When in DDC mode an additional trigger option is available: 'Magnitude Trigger'.

The magnitude trigger circuit calculates the magnitude of the real and imaginary parts by the following equation:

Post-Trigger Delay for magnitude trigger can be adjusted within the time interval from 0 to [(232 – 1) * block_size (samples)], where block_size is 16.

Pre-Trigger Delay for magnitude trigger can be adjusted within the time interval from -191 samples to 0.

Triggering is performed by comparison with a level and a hysteresis value. The hysteresis value may be used to avoid triggering on noise signals. i.e. A rising edge trigger will occur when the signal reaches the level value, having passed through level - hysteresis. Conversely for a falling edge, the trigger will occur at level having fallen through level + hysteresis.

Dwell Time

The potential trigger is further qualified by a dwell time which is specified in samples. Positive values of dwell indicate the number of samples that must be in the initial trigger state (e.g. below the low threshold for a rising edge trigger) before a trigger will be recognized. Negative values of dwell indicate the negative of the dwell time, which is the number of samples that must be in the second trigger state before a trigger is recognized.

It is easiest to explain the use of these values by several examples. Suppose the input signal is some kind of burst transmission, such as a TDMA signal consisting of a burst of signal with silence between the bursts. Note that even though in general the magnitude of the burst signal may be above our threshold, there can be samples in the middle of the burst whose magnitude is below our threshold. If we just used a rising edge trigger to try to capture the start of a burst, we might get false triggers if we happened to arm our trigger in the middle of a burst. In that case we might trigger later in the middle of the burst if any sample fell below our threshold. To guarantee triggering on the start of the burst, we might say that we won’t trigger until 20 consecutive samples are below the threshold (to detect the gap between bursts) and then trigger the next time a sample goes above the threshold. We would set this up by using a positive slope (slope=0) and a dwell value of +20. Then we would only trigger after the signal has been below the threshold for at least 20 samples and then rises above it.

Suppose we want to trigger on the end of the burst instead of the beginning. Then we would want to use a negative slope (slope=1) and a negative dwell value. If we set slope=1 and dwell = -20, then we would trigger only if the signal goes above the threshold (indicating that a burst is in progress) and then goes below the threshold for 20 consecutive samples (indicating the gap between bursts). Without the dwell time, we might erroneously trigger if a sample in the middle of the burst fell below the threshold.

Digital Down Conversion (DDC) Configuration

Configuration & Control

The M9703A Digitizer DDC operation is configured and controlled using the IviDigitizer class. The methods listed below are provided by the Keysight MD1 driver. Detailed help on these interfaces may be found in the separate help files shown in the table.

Driver | Methods / Interface | Attributes | Detailed help located
IVI-COM | IIviDigitizerChannelDownconversion | Enabled, Center Frequency, IQ Interleaved | MD1 IVI Driver Help
IVI-C | AgMD1_TriggerMagnitudeConfigure | Source, Level, Hysteresis, Slope
LabVIEW | Configure Downconversion.vi | Enabled, Center Frequency | MD1 LabVIEW Driver Help
 | Trigger Magnitude Configure.vi | Source, Level, Hysteresis, Slope

To enable and use DDC mode in the SFP Collapsed Soft Front Panel application, please refer to the MD1 SFP Collapsed Soft Front Panel Help.


Custom firmware capability (FPGA Development Kit)

The -FDK Collapsed FPGA Development Kit (FPGA Collapsed Field Programmable Gate Array Development Kit) option allows the access to the four on-board processing FPGAs for custom algorithm implementation.

The U5340A FPGA Collapsed Field Programmable Gate Array development kit can be used for implementing such algorithm for deployment on embedded systems using a HDL design entry approach.

For details, please refer top U5340A FDK Collapsed FPGA Development Kit product www.keysight.com/find/U5340A and U5340A FDK Collapsed FPGA Development Kit User Manual.


Keysight M9703A Hardware Extension of 89600 VSA Software

The 89601B: 89600 VSA software supports the Keysight M9703A AXIe High-Speed Digitizer. This VSA measurement hardware configuration offers broadband vector signal analyzer measurements up to 625 MHz of analysis bandwidth (model dependent).

Model | Bandwidth
M9703A-SR1 | 390 MHz
M9703A-SR2 | 625 MHz

That the M9703A is not supported by the earlier 89601A VSA software, neither by the 32-bit version of the current software i.e. You must use the 64-bit version of the 89600 VSA software with M9703A.

Configuring the 89600 VSA software application to use the M9703A hardware

  1. Start the 64-bit version of the 89600 VSA software application.
  2. Configure the M9703A digitizer as the VSA measurement input by creating an 'Analyzer Configuration' that uses the M9703A digitizer as the Logical Instrument (ADC Collapsed Analog to Digital Converter) by performing the following steps:

    1. From the menu, go to Utilities > Hardware > Configurations, and click on Add New Configuration button ( [image]). This will open the 'New Hardware Configuration' dialog.

    2. De-select 'Simulate Hardware' if it is selected.

    3. Select the M9703A digitizer from the list of 'Possible Logical Instrument' and drag it or click on the [image] button to add it to the 'Configuration' box.

    4. In the box below ensure that M9703A appears as the 'ADC Collapsed Analog to Digital Converter' entry, and if you have more than one M9703A connected - select the required unit using the drop-down list.
    5. You may either use the default name or specify another name for this analyzer configuration.
    6. Click OK to close the 'New Hardware Configuration' dialog.

    7. But before closing the 'Hardware Configurations' dialog, use the Current Analyzer Configuration drop-down to select the newly created M9703A Digitizer as the current item.

  3. Review and configure the Measurement Setup Parameters.

Multi-Channel Measurements

When using the M9703A digitizer in VSA configuration, the digitizer forms the measurement front-end data acquisition hardware for the 89600 VSA software. The M9703A digitizer supports single channel I+jQ, multi-channel Dual I + jQ, and cross channel measurement configurations. The analysis bandwidth and maximum sample rate depend on whether the digitizer model is M9703A-SR1 or M9703A-SR2.

Interleaved Mode

The option of using two channels of the M9703A in Interleaved mode is provided if your product has been ordered with the -INT option. This in effect provides double the sampling rate with the trade-off of halving the available center frequency range. As shown in the table:

Mode | Model Option | Center Frequency Range | Sampling Rate
Normal (Non-Interleaved) | -SR1 | 0 - 1 GHz | 1 GS/s
 | -SR2 | 0 - 1.6 GHz | 1.6 GS/s
Interleaved | -SR1 | 0 - 1 GHz | 2 GS/s
 | -SR2 |  | 3.2 GS/s

For best measurement fidelity you should ensure that the center frequency + analog bandwidth/2 does not cross the Nyquist frewquency.

Interleaved mode may be enabled by opening the Input > Extensions.. window from the menu bar. Then select the Enable Interleaving option, changes are applied immediately.

External Clock

The option of using an external sampling clock is provided. This clock must be continuously present if the mode is selected otherwise an error will occur. The range of clock input frequency is model dependent, as shown in the table below:

Model option | Frequency Range
-SR1 models | 1.8 to 2 GHz
-SR2 models | 1.8 to 3.2 GHz

To use this option, first connect an external clock signal in the accepted range to the CLK IN connector on the M9703A front panel. The signal must be in the range +5 to +15 dBm Collapsed Power measurement relative to 1 mW, P (dBm) = 10log10(1000.P).

Then open the Input > Extensions... window from the menu bar. Select the Enable external clock option, and double click the External clock frequency value to bring up the editing window. You may then set the value of the external clock frequency being applied. As shown below:

Force Software DDC

This function overrides the hardware processing which is normally performed by the M9703A, and forces the VSA software to perform the DDC operation. It is provided simply as a demonstration of the difference in performance between hardware DDC and software.

It can be enable as shown in the screen capture below by ticking the Force Software DDC option.

Measurement Setup Parameters:

This section provides measurement and parameter setup information which are specific to the 89600 VSA software when used along with the M9703A AXIe High-Speed Digitizer. This information will help you to properly setup the VSA in this hardware configuration to make measurements using the M9703A digitizer.

Alignment/Calibration:

If required, an internal calibration may be performed. Note that this operation may require several minutes to complete. Accessed from the menu Utilities > Calibration.

Channels:

From the menu Input > Channels, available options:

  • 1 channel through 8 channels,
  • I+jQ (IN1+jIN2)
  • Dual I+jQ (IN1+jIN2, IN3+jIN4)
  • Triple I+jQ (IN1+jIN2, IN3+jIN4, IN5+jIN6)
  • Quad I+jQ (IN1+jIN2, IN3+jIN4, IN5+jIN6, IN7+jIN8)

The custom channel configuration may be used to specify a non-standard mapping between the digitizer input and the VSA logical channel. The default mapping of logical channel to digitizer input is:

Logical Channel | Digitizer Input
1 | IN1
2 | IN3
3 | IN5
4 | IN7
5 | IN2
6 | IN4
7 | IN6
8 | IN8

From the menu Input > Analog the following parameters can be set:

Range: The M9703A digitizer has two range settings: 2 V (10 dBm Collapsed Power measurement relative to 1 mW, P (dBm) = 10log10(1000.P)) and 1 V (4 dBm Collapsed Power measurement relative to 1 mW, P (dBm) = 10log10(1000.P)).

Coupling: DC

Input Impedance: 50 Ohms.

Connection: Single Ended.

Frequency:

The frequency measurement parameters may be configured from the MeasSetup > Frequency menu.

Digitizer Model | Band | Center | Span | Start | Stop
M9703A-SR1 | 0 to 390.625 MHz | 195.3125 MHz | 390.625 MHz | 0 | 390.625 MHz
M9703A-SR2 | 0 to 625 MHz | 312.5 MHz | 625 MHz | 0 | 625 MHz
Span:

The maximum span is dependent upon the maximum sample rate of the particular M9703A digitizer model.

Model | Max span
M9703A-SR1 | 390.625 MHz
M9703A-SR2 | 625 MHz

ResBW: 3 MHz

Main Time Length: 1.273125 µs

Center Frequency Limits:

The limits depend on which model you are using:

Model | Limits
M9703A-SR1 | 0 to 1.0 GHz
M9703A-SR2 | 0 to 1.6 GHz

Frequency Counter: Not available.

Trigger

Trigger settings may be accessed via the Input > Trigger menu.

The following trigger parameters are available:

  • Style: Free Run*, External, and Magnitude**
  • Slope: available for External and Magnitude**
  • Level: available for External and Magnitude**
  • Delay: available for External and Magnitude**

Trigger levels:

Trigger Type | Level | Default
External | -5 V to +5 V | 2V
Magnitude** | 0 to 1.414 V | 10 mV

Trigger delays:

Trigger Type | Max Pre-Trigger Delay | Max Post-Trigger Delay
External | VSA increases the record size to make the pre-trigger delay fit (limited by the amount acquisition memory available). | 1 second
Magnitude** | –137 samples * sampling Interval | 1 second

*On "Segmented Capture" feature the free run triggered is not supported. (Segmented Capture feature may be accessed via the MeasSetup > Time menu)

**M9703A-DDC option is required for Magnitude triggering.

Trigger Holdoff: The trigger holdoff is not supported by the M9703A digitizer.

Soft Front Panel Control: The 'Disconnect' feature can be used to pause the VSA and release its control of the M9703A digitizer. Then the digitizer can be used independently from the VSA, for example, using the MD1 SFP Collapsed Soft Front Panel application. Independent control must be released before resuming VSA measurements. When returning to the VSA and starting or resuming a measurement, the VSA will restore the digitizer state that was set before disconnected.

Hardware: Set up an Analyzer Configuration with the M9703A digitizer as the Logical Instrument, as described in Measurement Configuration Setup.

Overlap: The M9703A digitizer does not support overlap processing. However, overlap processing is available during recording playback.

Preset: The default parameter settings that are different from the 'Preset Setup' settings are listed below. (Any parameters not listed here are set to the same value as Preset Setup.)

Recording: the VSA application enables time data recording from the M9703A digitizer to the PC's disk drive. The length of time waveform recording is limited by the memory available on the M9703A digitizer.

Setup Save/Recall: The M9703A digitizer state is not saved when the VSA application is closed. When a setup is recalled into the VSA, the M9703A digitizer state is set appropriately based on the recalled VSA setup.


Multi-Module Synchronization

Introduction

The M9703A AXIe Digitizer includes the ability to maintain synchronization across multiple modules within the same AXIe chassis. The modules are synchronized through AXIe local bus. This feature allows a modular acquisition system of up to 64 channels to be achieved, whilst maintaining phase coherence across all channels.

Figure 10 - An M9505A AXIe chassis with five M9703A Digitizers fitted

Depending on the chassis:

  • Installing two M9703Ain the M9502A 2-Slot chassis, up to 16 synchronized channels may be implemented.
  • Installing five M9703A in the M9505A 5-Slot AXIe chassis allows up to 40 channels to be synchronized (See above picture).
  • Installing eight M9703A in the M9514A 5-Slot AXIe chassis allows up to 64 channels to be synchronized.

Master/Slave Configuration and Trigger

The same trigger source configuration must be applied on the master and on the slave modules prior to synchronize the modules through the user's code.

Each group of synchronized modules shares a common trigger source. The trigger is then propagated to the slaves when the modules are synchronized together. The module providing the trigger source is defined as the Master, and the remaining modules are defined as Slaves. The master should be in the central slot position in the chassis of the synchronized modules.Therefore the physical layout of the chassis should be considered when configuring your system.

As with single module operation, the trigger source may be derived from any one of the (8) input channels (Internal Triggering), or from one of the three dedicated external trigger inputs (TRG 1, 2 & 3) located on the front panel or from the AXIe_SYNC signal.

The calibration of each module must be performed before synchronizing the modules together. After synchronization the module calibration is not available.

External Clock and Reference Clock

When used in Multi-Module mode, the Internal clock source is not allowed. The remaining sources (AXIe Reference, External Reference, External Clock) are available.

All modules must be set to using the same clock source prior to be synchronized.

Changing the clock source once the modules are synchronized is not possible.

Minimum Acquisition Size

The minimum allowed acquisition size in synchronized mode is 3000 samples.

Configuring the M9505A or M9502A AXIe chassis for Multi-Module Synchronization

The M9505A or M9502A AXIe chassis must be configured to route the TRIG 0 signal to the SYNC signal in order to operate in Multi-Module mode. You must also ensure that 'Sync routed through crosspoint switch' is ticked.

Once any changes have been made, do not forget to click on the Apply Changes button.

You probably want to click on the Save Trigger Routing as Default State so that this settings are preserved on AXIe chassis power cycles.

This may be done using the AXIe chassis web interface (as shown below). The web interface (M950x5 SFP Collapsed Soft Front Panel) may be opened from Keysight Connection Expert.

Figure 11 - AXIe chassis web interface, showing SYNC option

Configuring the M9514A 14-slot AXIe chassis for Multi-Module Synchronization

Example of configuration:

  • M9514A – 14 slot chassis
  • M9521A - ASM card
  • HPZ400 desktop PC running Windows 7 - 64
  • M9048A PCIe adapter (connected into slot 5)
  • Two M9703A digitizers connected into slot 5 & 6 of the M9514A chassis
  • MD1 version 1.14

System configuration sequence

A. Configuring the M9514A 14-slot AXIe chassis without the M9703A cards

1. Install the IO Libraries 17.1 on the desktop PC

2. Install the M9521A ASM card into the system slot of the M9514A chassis (slot 7)

3. Connect the M9521A ASM to the desktop PC using the M9048A PCIe adapter

4. Power up the M9514A chassis (without the M9703A cards)

5. Wait until the status LED of the M9514A chassis and ASM are both solid green, then power up the PC

6. Install the M9514A chassis driver & SFP Collapsed Soft Front Panel from the CD-ROM, revision A dated from March 2014

7. Install the M9521A ASM driver & SFP Collapsed Soft Front Panel from the CD-ROM, revision A dated from March 2014

8. Open the Windows Device Manager, it shows that an Ethernet Controller was not correctly configured. As indicated in the M9521A ASM Startup Guide, installe an Intel PROWin network driver (ProWinx64.exe under Windows 7 64 found at the following link: https://downloadcenter.intel.com/download/18713)

9. Restart the PC

10. The Device Manager shows that the M9521A ASM is correctly installed under "Agilent/Keysight-VISA Modular Devices".

11. Open the Keysight Connection Expert, and check that the M9521A and M9514A correctly are detected.

For the M9514A (see M9514-5.png), the firmware version is: F14AX-2.3.11

and the IVI driver version (32 & 64-bit) is: 1.0.17.0

For the M9521A (see M9514-6.png), the firmware version is: asm-2.3.11

and the IVI driver version (32 & 64-bit) is: 1.0.17.0

Note that if the M9514A chassis doesn't show up in the Instruments menu of the Keysight Connection Expert and shows up with an incorrect IP address (like 0.0.0) in the PXI/AXIe Chassis menu, check that the Self Manager Lan switch on the front panel of the M9514A chassis is in the default ASM (right) position. You can also try a chassis IP Reset on the front panel of the M9514A chassis and the restart the PC (see M9514_M9521_User Guide for more information).

12. Check that you can control the M9514A chassis and M9521A ASM card through the M9514A SFP Collapsed Soft Front Panel and M9521A SFP Collapsed Soft Front Panel

Note that if the Connect to AXIe System Module window doesn't show any devices when the Simulation Mode check box is cleared, you can copy the VISA Address of the module from the Keysight Connection Expert into the Selected Module box and click on Connect:

For example, the VISA address of the M9521A ASM card in the Keysight Connection Expert shows up as:

You can copy and paste the VISA address into the Selected Module box of the M9521A SFP Collapsed Soft Front Panel and click on Connect to launch the SFP Collapsed Soft Front Panel:

13. Install the MD1 software

14. Power down the M9514A chassis .

B. Configuring the M9514A 14-slot AXIe chassis with the M9703A cards

1. Install the M9703A in the M9514A chassis

2. Power up the M9514A chassis (wait the status LED are solid green on the chassis and M9521A ASM) and power up the desktop PC

3. Check that the M9703A cards are correctly detected in the Device Manager, Keysight Connection Expert and in the MD1 SFP Collapsed Soft Front Panel.

C. Configuring the M9514A 14-slot AXIe chassis for Multi-Module Synchronization

The AXIe chassis must be configured to route the TRIG0 signal to the SYNC signal in order to operate in Multi-Module mode.

Open the M9521A SFP Collapsed Soft Front Panel, connect to the M9521A ASM connected into the chassis.

Note that if the Connect to AXIe System Module window doesn't show any devices when the Simulation Mode check box is cleared, you can copy the VISA Address of the module from the Keysight Connection Expert into the Selected Module box and click on Connect.

1. Configuring the CrossPoint Switch:

In the Crosspoint Switch tab Connections,

  • clear the Allow Control check box.
  • connect the TRIG0 Trigger Bus Input to the CS_SYNC Trigger Bus Output.

2. Configuring the backplane:

In the Menu Configure > Configure Backplane Sync...,

  • set the Backplane Sync signal (BP_SYNC), to MultiFrame Output Sync (MO_SYNC)

3. Saving the current ASM configuration as the power-on state:

In the Utilities -> Manage State

  • select Save As Power-On State

Mode of operation

Once the modules and chassis are configured, the multi-module acquisition can be performed.

For an example of user code, please contact Keysight technical support http://www.keysight.com/find/assist.


Electrical & Environmental Specifications

For full specifications, please refer to the product data sheet which may be found on the CD which came with your product, or from the Keysight Technologies website: www.keysight.com/find/M9703A


Programming Information

This section provides general programming advice and specific information regarding the use of the Keysight drivers.

The AgMD2 API documentation can be found in Start > All programs > Agilent > MD1 Digitizer > MD1 Help

Program examples can be found in Start > All programs > Agilent IVI Drivers > AgMD1 Digitizer > Example

Driver update

Firmware Initialization


Driver update

For users who have already installed the driver MD1 1.13.x release it is recommended to switch to release 1.14 providing important updates.

After installing Driver MD1 release 1.14, user may have to restart the computer twice to be able to use the instrument. (Otherwise, Windows could report "This device cannot start. (Code 10)").


Firmware Initialization

The on-board FPGA Collapsed Field Programmable Gate Array’s (field-programmable gate arrays) contain processor logic needed to efficiently execute several crucial functions. They will be automatically programmed at startup before calibration.

The name for the FPGA Collapsed Field Programmable Gate Array program file is a synthesis of model, FPGA Collapsed Field Programmable Gate Array destination, and option information. The file name suffix is always ".bit". The automatic initialization - mentioned above and for all subsequent demands for this module (in particular this applies when changing the acquisition mode or using the UserDpuA, UserDpuB, UserDpuC, UserDpuD string options in FDK Collapsed FPGA Development Kit mode) - will load the FPGA Collapsed Field Programmable Gate Array files as follows:

- The driver will search the current directory for the desired FPGA Collapsed Field Programmable Gate Array program file.

- If it is not found, the driver will search for the file "AgMD1Fundamental.ini" in the current directory first, then in the directory pointed to by the environment variable "IVIROOTDIR32" or “IVIROOTDIR64”.

-The "AgMD1Fundamental.ini" file should contain the name of a directory which will also be searched for the appropriate FPGA Collapsed Field Programmable Gate Array files. Here is a typical example of its contents:

[Paths]

fpgaPath=C:\Program Files (x86)\IVI Foundation\IVI\Drivers\AgMD1\Firmware

GeoMapPath=C:\Program Files (x86)\Agilent\MD1\Bin\

CALPATH=C:\ProgramData\Agilent\MD1\Cal


Utilities

This section describes supplied programs which may be used to configure various aspects of your instruments:

Firmware Upgrade Utility


Firmware Upgrade Utility (AcqEepromProg)

The EEPROM programming utility (AcqEepromProg.exe) is used to load either instrument options or firmware to your Keysight instrument.

Updating the M9703A Control FPGA Firmware

The control FGPA of the M9703A performs the management and control functions of the digitizer. Its firmware may be updated via the host PC. You may be asked to perform this operation by Keysight Technologies support personnel as required. To perform this upgrade please follow the procedure below:

  1. Launch the upgrade utility - AcqEepromProg.exe from : C:\Program Files (x86)\Agilent\MD1\bin
  2. Select the M9703ACTRL.mcs file from the folder : C:\Program Files (x86)\IVI Foundation\IVI\Drivers\AgMD1\Firmware
  3. Select the target device. The EEPROM upload process will start, and may take up to 10 minutes to complete.
  4. Once finished, close the application.

DO NOT STOP THE PROCESS during the update. Doing so may cause damage to your module.

AcqEpromProg General Information

Syntax:
AcqEepromProg.exe [-eeprom | -maincpld] [sn:<serial>] [efw:<eepromNumber>] [<filename>]

All of the listed switches are optional, please see the notes below for details.

Filename conventions

Files with the ".epr" extension contain instrument options and are generated by Keysight for a specific instrument serial number, they may not be used on instruments with other serial numbers. These files must be loaded to the device Option EEPROM.

Files with the ".vme" or ".svf" extension contain instrument operating firmware generated by Keysight, but may be used on any instrument of the appropriate model type. These files must be loaded into the instrument Firmware EEPROM or CPLD

If one or mores spaces appear in the filename or path, the double quotes are required on the filename string as shown in the examples below.

It is not possible for the utility to check that the file is suitable for the FPGA Collapsed Field Programmable Gate Array / CPLD of the specified device, so please use this mode carefully. Programming a device with the incorrect firmware file may render it unusable.
However, as long as the device has not yet been re-booted (power cycled) it will be possible to re-write the correct file. Conversely, if the device has been incorrectly programmed and subsequently re-booted, it will be necessary to return it to an Keysight Service Center for recovery.

Available Switches
Switch | Function
-eeprom | Specifies that the firmware file should be loaded into the device Option EEPROM
-maincpld | Specifies that the firmware should be loaded into the main Firmware EEPROM / CPLD of the instrument
efw:<eepromNumber> | Specifies the Firmware EEPROM number for the firmware to be loaded into. Valid values are '0' or '1'. The value '1' is only supported by the U1084A instrument, and only valid when preceded by -maincpld
sn:<SerialNumber> | Specifies the module to program based on it's serial number. Useful where multiple modules are connected to the host.
Usage examples:
AcqEepromProg.exe

Opens a file dialog box, then loads the content of the chosen file into the EEPROM/CPLD-FPGA Collapsed Field Programmable Gate Array of a defined device. If the chosen file has a ".epr" extension, the application will load the file into the Options EEPROM of the device that matches the serial number in the file.

If the chosen file has a ".vme" or ".svf" extension, the application will prompt the user for a target device when there are several devices connected. If there is only one device, that device will be chosen without prompting.

AcqEepromProg.exe <filename>

example:

AcqEepromProg.exe DC271_CH12345.epr

Loads the content of the file 'DC271_CH12345.epr' into the Options EEPROM of the specified device. If there is only one device, that device will be chosen without prompting. When several devices are connected, the application will prompt the user for a target device.

AcqEepromProg.exe -eeprom <filename>

example:

AcqEepromProg.exe -eeprom U1084A_CH12345.epr

Loads the content of the file 'filename' into the Options EEPROM of the specified device. The serial number in the file is used to find the proper target device. The serial number encoded in the options file must match the serial number of the target device.

AcqEepromProg.exe -maincpld <filename>

example:

AcqEepromProg.exe -maincpld "C:\Program Files\IVI Foundation\IVI\Drivers\AgMD1\Firmware\U1084_dig_02380181.vme"

Loads the content of the file 'filename' into the main Firmware EEPROM / CPLD of the specified device. If there is only one device, that device will be chosen without prompting. When several devices are connected, the application will prompt the user for a target device.

AcqEepromProg.exe -maincpld sn:<serial> <filename>

example:

AcqEepromProg.exe -maincpld sn:12345 "C:\Program Files\IVI Foundation\IVI\Drivers\AgMD1\Firmware\m9202_ddc_020000381.vme"

Loads the content of the file 'filename' into the main Firmware EEPROM / CPLD of the specified device.

AcqEepromProg.exe -maincpld dev:<number> -efw:<eepromNumber> <filename>

example:

AcqEepromProg.exe -maincpld dev:1 efw:1 "C:\Program Files\IVI Foundation\IVI\Drivers\AgMD1\Firmware\U1084_dig_02380181.vme"

Loads the content of the file 'filename' into the Firmware EEPROM specified by 'eepromNumber'. The option 'efw' only supports values 0 or 1 and the value 1 is only supported on U1084A instruments.

Requires:
  • QtCore4.dll
  • Qt3Support4.dll
  • QtGui4.dll
  • AgMD1Fundamental.dll
Licensing:

The compiled code used to achieve the 'AcqEepromProg.exe' functionalities are provided in source code from the Lattice 'ispVM(r) Software' package. The use of this compiled source code is subject to conditions, as explained in the section 2.C of the 'Lattice Standard License Agreement.txt' file, which is an integral part of this package.

Copyright (C) 2004, 2005-2012 Keysight Technologies, Inc.


Accessories

U1092A-HVS SMA Input Over-voltage Protection


U1092A-HVS SMA Input Over-voltage Protection

This overvoltage protection kit allows the digitizers with 50 Ohm input (not high-impedance input models) to withstand a high voltage surge of up to 5 kV.

The overvoltage protection kit contains 2 parts:

  • A 3dB SMA Attenuator
    • Length: 22 mm
    • Diameter: 7.1 mm
    • Weight: 4 g
  • A 90 V SMA Spark Gap
    • Length: 39.5 mm
    • Diameter: 15.3 mm
    • Weight: 20 g
Specifications
Parameter | Value
Frequency range | DC to 1 GHz
Input impedance | 50 Ω
Attenuation | 3 dB
VSWR (DC to 1 GHz) | < 1.25
Impulse discharge current (8/20 us pulse) | 10 kA

Install the Attenuator and Spark Gap as shown in the diagram below:

Figure 12 - PXIe module with Input Over-voltage protection fitted

Both the Spark Gap and the Attenuator MUST be used together in order to fully protect the modules.

In order to limit the input current, the Attenuator MUST be inserted between the Spark Gap and the input of the module.